Programmable sense amplifier delay (PSAD) circuits are known in the art of circuits for semiconductor memory array chips and are utilized to delay the output of a sense amplifier until the sense amplifier has finished sensing the data of a cell of a memory array. This is shown in FIG. 1 to which reference is now made.
The memory array 10 has a cell 12 that is to be read by a sense amplifier 14. The sense amplifier 14 determines the value of the data in the cell 12 by comparing its value to two reference values, "REF1" and "REF0" and producing an output signal, DAT. The output signal DAT is then passed through a trip inverter 16 before being latched by a latch 18.
Because the output signal DAT is invalid until the sense amplifier 14 has finished sensing the data in the cell 12, the trip inverter 16 is shorted by a switchable line 20 having a switch 22 therein. During sensing, switch 22 is closed and line 20 connects the output of trip inverter 16 with its input. The result is that the output signal DAT is maintained at a middle voltage between the two reference values. When sensing is finished, switch 22 is opened and the output signal DAT is allowed to propagate to latch 18.
Switch 22 is controlled by a PSAD 24 whose delay is programmable and is typically set to approximately match the sensing time of the sense amplifier 14. As shown in the timing diagram of FIG. 2, to which reference is now made, an "EQ" signal is generated when an address signal is received. The EQ signal prepares both the array 10 and the PSAD 24 (which typically receives the complement EQB signal) for sensing. Upon the fall of the EQ signal, the sense amplifier 14 begins sensing and the PSAD 24 begins measuring the time. FIG. 2 indicates that the DAT signal out of the sense amplifier 14 is ready slightly before the INR signal out of the PSAD 24 and thus, the data of cell 12 will be read only once it is ready.
Since the chip of the memory array can operate under a wide variety of temperatures and some variety of input voltage levels, the PSAD delay must be set to cover all possibilities. Typically, for an electrically programmable read only memory (EPROM) array, this is done by determining the delay for the worst combination of temperature and voltage level. This provides the maximal delay, but not the optimal delay, per sensing condition.
For FLASH electrically erasable programmable read only memory (EEPROM) arrays, this is not possible. FLASH EEPROMs effect an erase by programming all cells to a known high value, providing a pulse of negative voltage and then sensing to determine if the cells now store a low value. Further negative pulses are provided only if the cells have not changed value. Since sensing defines the point where erasure stops, if erasure occurs at one temperature and voltage level and the chip is then utilized (read and programmed) at another temperature and voltage level, it is possible that the erasure might not be complete for the second sensing condition. This happens if the variation with respect to temperature and voltage supply Vcc of the PSAD delay is different from that of the sensing time. In this case, the data written therein might not be readable at the second sensing condition.
U.S. Pat. No. 4,894,561 to Nogami describes a CMOS inverter which has compensation for temperature and voltage variations.